1. Field of the Invention
The present invention relates to semiconductor fabrication.
2. Description of the Related Art
In the fabrication of semiconductor devices such as integrated circuits, memory cells, and the like, a series of manufacturing operations are performed to define features on semiconductor wafers. The semiconductor wafers include integrated circuit devices in the form of multi-level structures defined on a silicon substrate. At a substrate level, transistor devices with diffusion regions are formed. In subsequent levels, interconnect metallization lines are patterned and electrically connected to the transistor devices to define a desired integrated circuit device. Also, patterned conductive layers are insulated from other conductive layers by dielectric materials.
The series of manufacturing operations for defining features on the semiconductor wafers can include an electroplating process for adding material to the surface of the semiconductor wafer. In the electroplating process, an electrolyte is disposed between an anode and the wafer surface to be electroplated. Additionally, the wafer surface to be electroplated is maintained at a lower voltage potential than the anode. As an electric current flows through the electrolyte from the anode to the wafer surface, electroplating reactions occurring at the wafer surface cause material to be deposited on the wafer surface.
Material deposition characteristics across the wafer surface are dependent on many parameters associated with the particular electroplating system and process. For example, parameters affecting the electrical current profile across the wafer can influence the material deposition characteristics. Also, parameters related to establishment of electrical contact with the wafer can influence the material deposition characteristics.
In view of the foregoing, there is a continuing need to improve electroplating technology as applicable to material deposition during semiconductor wafer fabrication.